A. Field of the Invention
This invention relates to data processing systems which include computing devices, and more particularly to an improved method and means for checking the normalizing operations in the arithmetic units of said computing devices.
B. Prior Art
A related application also assigned to the present assignee, is U.S. Ser. No. 221,981, filed Dec. 28, 1982, now U.S. Pat. No. 4,366,548, and entitled "Adder for Exponent Arithmetic" by Glen R. Kregness and Peter B. Criswell. Mr. Criswell is the sole inventor of the present device. Portions of that application have been included herein to provide the common background environment and explanatory description for the present invention.
In computing devices employing floating-point arithmetic capability, the data or operands upon which arithmetic functions are to be performed are in a format such that one portion of the data word contains the actual information and is called the mantissa. A second portion of the data words contains the signals indicative of the relative position of the arithmetic point, such as decimal or binary point, of the information contained in the mantissa, and is referred to as the characteristic. To perform arithmetic operations on data on the floating-point format, the actual arithmetic operations are performed on the signals of the mantissa portions of the data words, and the characteristics are used primarily to indicate the relative positions of the floating-point operands under consideration, and are utilized in determining the characteristic of the result of the arithmetic operation. For example, in adding two floating-point operands, each having its own characteristic and mantissa, the arithmetic section of the data processing system utilizes the two characteristics to determine the actual digit-by-digit alignment of the mantissa portions in preparation for perfoming the floating-point arithmetic operation. For an add operation, the aligned mantissas are added together to form a new floating-point mantissa, and a resultant floating-point word is generated as a result of the combination of the newly formed mantissa with the characteristic. Floating-point subtraction, multiplication, division, or format conversion, all involve manipulation of the characteristic. Normalization is the process of shifting the mantissa and adjusting the characteristic such that the most significant bit of the mantissa appears in a certain position.
The floating-point data words are stored, transferred, and processed, via a plurality of multiple-bit registers. Each bit position of a register represents a power of the radix of the register, and the modulus of the register is the radix raised to the power indicated by the number of bit positions of the register. For example, a 1's complement six-bit register has a modulus 2.sup.6, with the least singificant bit position having a value 2.sup.0, with each increasing bit position having a value of 2 raised to the power designated by the bit position. For use with operands in floating-point format, the registers must utilize sufficient bit positions for holding the representation of the mantissa and the characteristic. For single-precision format, the entire operand comprised of the sign, characteristic, and mantissa, is contained in a single register, however, the portion devoted to the mantissa is independent of the portion devoted to the characteristic. These entities are handled substantially independently.
The bit capacity of registers in the data processing system often relate to the number of bit positions in the memory registers. Operands in the floating-point format that are contained within the number of bit positions of a memory register capacity are often referred to as single-precision floating-point operands. The limitation of the number of bit positions to a single register obviously places limitations on the capacity and precision of the arithmetic manipulations. In order to increase the capacity of the floating-point operands, systems have been developed that utilize two full operands to comprise a single floating-point operand. This effectively doubles the bit capacity, and is commonly referred to as double-precision floating-point operation. In the double-precision format, the characteristic often times utilizes more bit positions than would be utilized for the single-precision format. In computing systems that utilize both single-precision and double-precision formats, systems have been devised for converting floating-point operands between the two systems of representation. For those systems that utilize a different number of bits positions to represent the characteristics between single-precision and double-precision, it is necessary that the conversion between formats provide for adjustment of the characteristic representation. Further, it is necessary that there be adjustments of the mantissa when the conversion is from double-precision to single-precision format, it is common to require that the number of the characteristic bits be reduced, and that certain bit positions in the mantissa be dropped. During the converse conversion, the number of bit positions of the characteristic is increased, and the additional number of bit positions of the mantissa is made available.
Both the characteristic and mantissa for floating-point arithmetic operations, whether they be single-or double-precisions may represent positive or negative values. The sign bit references represents the sign of the mantissa. To avoid using two separate sign designations, that is, one for the characteristic and one for the mantissa, within the same operand, a system of characteristic biasing has been developed to indicate the sign of the characteristic. For example, a single-precision floating-point operand that provides for an eight-bit characteristic, can express numerical values ranging from 0 through octal 377. By arbitrarily applying a bias of octal 200 to the actual characteristic, the zero point is effectively shifted and permits the numerical representation of minus octal 200 through octal 177. In this manner, the value of the characteristic indicates whether it is positive or negative, with those characteristic values having a numerical value of octal 200 or less, representing negative characteristic values. A similar biasing system is applied to double-precision characteristics, with the same purpose. For example, if an eleven-bit characteristic is utilized, a bias of octal 2000 establishes a mid-point with numerical values of octal 2000 or less being of a negative value and characteristic values of more than octal 2000 being of a positive value. It can be seen, of course, that when converting between a single-and double-precision formats, the biasing as well as the bit capacity must be adjusted.
In performing conversion from double-precision floating-point to single-precision floating-point, care must be taken to establish that the magnitude of the double-precision characteristic can be expressed in a number of bit positions available in the single-precision format. In the event that a double-precision floating-point characteristic has a numerical value greater than the upper positive range of the single-precision floating-point characteristic, an overflow fault will occur, and an indication of this failure should be provided. Similarly, a double-precision floating-point characteristic on the lower extremity of the range that extends beyond the bit capacity of the single-precision floating-point operand cannot be accurately converted, and will cause an underflow fault to occur. The characteristic biasing system, the conversion from double-precision floating-point to single-precision floating-point and for conversion from single-precision floating-point to double-precision floating-point is described in detail in U.S. Pat. No. 3,389,379 to G. J. Erickson, et al.
When adding or subtracting to floating-point operands, it is necessary that each of the mantissa portions be aligned so that bit-positions having similar weights will be properly added. This alignment shift is called normalization and is determined by the examination of each of the characteristic postions.
Typically, within the arithmetic section of the Instruction Processor of present day data processing systems, certain instructions required a normalizing process on either the input operand directly (such as a scale factor shift) or on the result of an operation on floating-point numbers (e.g. floating point add) to normalize the mantissa before packing the characteristic.
Usually, the hardware to accomplish this included a normalizer module which determined the shift count and the direction needed to normalize a 36-bit or a 72-bit operand to a particular bit. The operand was then shifted within a shift matrix by the amount and in the direction indicated by the normalizer module. In all of these known earlier systems, however, this normalization process was never throughchecked. That is, there was never an overall check made to determine whether the normalization indicated was, in fact, accomplished.